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The performances are quite acceptable for a complete receiver with a noise figure budget up to 20 dB. Since the low noise amplifier is single-ended, a single balanced active mixer is used to save power consumption.


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Shown in Figure 6 , the topology in this design is quite conventional and the major task here is the proper sizing of these devices to achieve low power consumption subject to acceptable gain and linearity the noise figure of the active mixer is not an issue compared with a passive one. The gain of the mixer is linearly proportional to the trans-conductance of the transistors MN2 and MN3 and the reload resistance of the mixer.

Using the biasing current of 0. For the linearity, it is mainly decided by the biasing condition of the MOS transistor. With regard to the low data-rate in this work, the IF frequency is set to 2. The signal is amplified with an IF amplifier with programmable gain control. The design is a conventional MOS switch-based amplifier [ 13 ]. By controlling the biasing condition and switching of different loads. The amplifier has a tuning range of 30 dB in gain. The frequency synthesizer has been a major bottleneck of fully-integrated transceivers [ 14 , 15 ]. Due to this large silicon area and power consumption, it is usually an off-chip sub-system in many ultra-low-power solutions.

However, in this work, to ensure the robustness and maximized flexibility, it is designed as a fully-integrated sub-system which provides frequency outputs fractional to the reference clock. It includes a voltage-controlled oscillator, a fractional-N frequency divider, a phase-frequency detector, a charge pump and a loop filter as shown in Figure 1.

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The voltage-controlled oscillator is the key building block in terms of working range, phase noise, and output power of the PLL. The key considerations are acceptable phase noise with low power consumption and small silicon area. The optimization is mainly focused on the high-performance LC tank. The oscillator has a start-up condition which is determined by the quality of the tank and the negative G m to compensate the tank loss, which suggests that low power is only possible for a high quality factor Q tank. A high Q can be obtained using an off-chip inductor, but it is susceptible to additional parasitic effects in the package and on the PCB.

In this work, properly sizing of this on-chip fully-symmetrical inductor is used to ensure a high-quality factor around 10 at the desired frequency range. The overall quality factor of the LC tank is about 6—7. After optimization, the biasing current of 0.

In additional to the varactors for continuous frequency tuning, a three-bit digitally-controlled capacitance bank is implemented so that the proposed VCO can work properly from 2. The output power of this VCO with an output buffer is around 3 dBm. Another key building block is the frequency divider. Another key consideration is the power consumption [ 14 ].

In this work, the blocks in the frequency divider are designed to be power efficient at the certain working frequencies. The prescaler is the most challenging building block in the frequency divider since it works at the highest operating frequency. However, it is quite power consuming compared with dynamic digital logic such as true-single-phase-clock TSPC. Therefore, it is preferred that the MCML circuit is only implemented at the highest operating frequency, while the lower frequency division is performed with single-ended logic. In this work, to maintain a good balance between operating frequency and power consumption, the input signal is firstly divided by two using a MCML divider followed by a differential-to-single-ended buffer CML-Dig in Figure 9.

The voltage swings of the input and output of the divide-by-two unit are about mV peak-to-peak.


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After a MCML-to-digital buffer, which is a differential to single-ended unit, the output becomes a rail-to-rail signal. Since the output frequency is now about 1. The total division ratios are determined by four bits of modulus control signals, which are connected to a sigma-delta modulator. In this system, the modulator is of three stages in Mash each of which is a bit configuration. Using this fractional-N topology, it is able to achieve division ratios which is a fractional, instead of an integer, number. It is now possible to use a higher reference clock for the PLL system, which results in fast settling time and maximized functionality.

The other building blocks in the PLL, as shown in Figure 10 , are quite conventional. A third-order RC-based loop-filter is used for better suppression of the reference spurs. In this work, key consideration is that the capacitor should be small enough to have a fully-integration solution. The parameters of the components in the loop filter are determined by the closed-loop transfer function of the PLL [ 15 ].

The whole PLL system is now a fourth-order system [ 13 ]. Since the gain of the VCO frequency tuning, operating frequency, division ratio, and charge current have been determined, the PLL has the freedom in optimization of loop filters. As the key target is the silicon area which is occupied by the loop capacitor.

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Simulation suggests that the proposed PLL is able to work at 2. In addition to the key building blocks, there are also some other circuits in the proposed system. The most important part is serial peripheral interface SPI circuit, since many circuits in the system are configurable. Accordingly, the working bands of the voltage controlled oscillator should be adjusted to support the desired operating frequencies.

The SPI has 32 bits, while 24 of them are used to control the transceiver. D0—D2 are used to control the cap array. D3—D4 control the frequency division of the integer divider. D5—D14 control the frequency division of the fractional divider. D15 is the enable bit of PLL. D16—D19 are used to switch the gain of the IF amplifier. D20 enables the receiver. D21 enables the power amplifier. D22 enables FSK modulate of the transmitter.

D23 enables FM modulate of the transmitter.

Low-Power CMOS Design for Wireless Transceivers

By designing SPI circuit, all of the control bits can be set by several on-chip registers. Finally, as a complete chip, it includes some functional building blocks, such as the biasing circuits, crystal buffer, and decoupling capacitors. The crystal buffer is designed to support an off-chip crystal of 20 MHz to meet 2.

De-coupling capacitors between the supply voltage and ground are added as many as possible to improve the noise performance. Implemented using a 0. The proposed transceiver is fabricated using a 0. Figure 12 shows the die photo of the transceiver, which is packaged in a QFN form for measurements. The first step of measurement is to set up the initial status of SPI with determines the working conditions of the circuits; for example, the phase-locked loop of this chip.

The output frequency of the PLL, f out is given by:. The VCO free running frequency should be close to the targeted 2. The matching network for the RFIO port is as follows. The inductance value can be from 2. Moltchanov, M.

Komar, A. Antonov, P. Kustarev, S. Rakheja, and Y. Pujari, S. Li, S. Farzaneh, S. Rakheja, P.